Semiconductor integrated circuit chips (hereinafter "IC chips") typically are mounted to and communicate via a chip carrier formed from a ceramic (e.g., alumina), an epoxy-glass (e.g., an organic epoxy) or a glass-ceramic. To allow interchip communications, metallic signal lines are provided within the chip carrier that interconnect the pads or pins of the chips mounted thereon.
Due to loading from a combination of chip/chip package resistance, inductance and capacitance, carrier mounted chips operating at high clock rates (e.g., about 500 MHZ to 1 GHZ) typically communicate with other carrier mounted chips at a maximum rate of about 50% of each chip's clock rate (e.g., about 250 MHZ to 500 MHZ). Often significantly lower communications rates must be employed at a significant bandwidth loss. Interchip wiring length differences also limit maximum interchip communications rates for carrier mounted chips (e.g., due to distortion/skew concerns). Accordingly, a need exists for a method and apparatus for increasing interchip communications rates.